The fabrication of integrated circuits (ICs) involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The devices are interconnected, enabling the IC to perform the desired functions. Interconnections are formed by, for example, forming contacts in a dielectric layer using, for example, damascene technique. The damascene technique, for example, forms a via or contact hole in the dielectric layer. The via serves as a contact to a device.
As technology advances, it is desirable to increase the speed of the device without impacting its reliability. Thus, larger via contacts are desired to lower contact resistance to improve the speed and it is important for via contacts to be coupled properly with the underlying contact regions on the substrate. However, as devices continue to shrink, separation distance between adjacent devices as well as separation distance between silicide contacts on the contact regions and adjacent gates is also reduced. Although larger via contacts may lower contact resistance, it may also lead to contact to gate electrical shorts or bridging between adjacent gates. These phenomena adversely render the IC malfunction.
Existing methods to avoid the problems above are not efficient and suffer from several disadvantages. As such, it is desirable to provide a device which is devoid of the above-mentioned problem, thus increasing the reliability of the IC. It is also desirable to provide an efficient and cost effective process for forming the device.